Thin-film transistors (TFT) have been widely used for (i) circuit elements for controlling switching of pixels of liquid crystal display devices (LCDs), (ii) circuit elements for configuring LCD drivers, and (iii) the like. In recent years, there have been demands for improvements in the quality/performance of LCDs such as large screens, high resolutions, and high frame rates. Accordingly, TFTs are increasingly required to deliver high performance and to be highly reliable.
Patent Literature 1 discloses a configuration of a bottom-gate type (inverted staggered type) TFT.
FIG. 14 is a cross-sectional view illustrating the configuration of the conventional bottom-gate type (inverted staggered type) TFT. The TFT has such a configuration that a gate electrode 302 is provided on a substrate 301, and, on top of the substrate 301 and the electrode 302, (i) a first insulating film 303, (ii) an oxide semiconductor 304 as a channel layer, (iii) a second insulating film 305 for serving as an etching-stopping layer, (iv) a source electrode 306, and (v) a drain electrode 307 are provided.
Additionally, in recent years, display devices have been developed, which include optical sensor circuits positioned corresponding to pixels so as to have image-sensing functions as well as image-displaying functions (see Patent Literature 1 for example).
Patent Literature 2 discloses a single-transistor optical sensor circuit.
FIG. 15 is a circuit diagram illustrating a configuration of an image display device including a conventional optical sensor circuit.
As illustrated in FIG. 15, an image display device 110 has display sections 112 and sensor sections 113 both arranged in matrix form. The display sections 112 and sensor sections 113 are defined with signal lines S101, S102, S103, S104 . . . and gate lines G101, G102 . . . , which signal lines and gate lines intersect each other.
The display section 112 is provided with TFTs 114 for driving respective pixels. The sensor section 113 is provided with a diode 115 and with a Tr 116 which is a circuit for amplifying an output from the diode 115. The display section 112 and the sensor section 113 are thus provided with the three types of functionally differing transistors.
A gate electrode 115G of and a source electrode 1155 of the diode 115 are connected to a photodiode resetting wire RST. A drain electrode 115D of the diode 115 is connected to a gate electrode 116G of the Tr 116 across the source wire S102, the source wire S103, and an output bus line Vout. A source electrode 1165 of the Tr 116 is connected to a power supply bus line Vs. A drain electrode 116D of the Tr 116 is connected to the output bus line Vout which is provided in parallel to the signal line S101.
A terminal 141a, which is one of two terminals of a boost capacitor, is connected to the drain electrode 115D and to the gate electrode 116G. The other terminal 141b of the boost capacitor is connected to an optical sensor line selecting wire RW.
FIG. 16 is a plan view illustrating a circuit board in which each transistor of the image display device 110 is configured in a bottom gate structure.
That is, the TFTs 114, the photodiodes 115, and the Trs 116 are each configured in a bottom gate structure.
In the image display device 110, horizontal lines (i), as a bottom layer, intersect vertical lines (ii) as a top layer, which horizontal lines (i) include gate lines G101, G102 . . . , an optical sensor line selecting wire RW, a photodiode resetting wire RST, and a supplemental capacity wire Cs, and which vertical lines (ii) include signal lines S101, S102, S103, S104, a power supply bus line Vs, and an output bus line Vout.
A gate electrode 115G of the diode 115 is an extending part of the photodiode resetting wire RST, and is connected to a source electrode 1155 via a contact hole 117. A drain electrode 115D of the photo diode 115 is provided on the same layer on which the source electrode 1155 is provided, and is connected, via a contact hole 118, to an extending part of a terminal 141a which is one of two terminals of a boost capacitor provided on the same layer on which the gate electrode 115G is provided. The terminal 141a (i) intersects, from beneath, the signal line S102, the signal line 103, and the output bus line Vout and (ii) is connected to a gate electrode 116G of the Tr 116.
The terminal 141b, which is the other terminal of the boost capacitor, is provided on the same layer on which the source electrode 115G and the drain electrode 115D are provided. The terminal 141b is connected, via a contact hole 119, to an extending part of the optical sensor line selecting wire RW.